[^:]*: Assembler messages:
[^:]*:3: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,q1,q2'
[^:]*:4: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,q1,q2'
[^:]*:5: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,q1,q2'
[^:]*:6: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,r2'
[^:]*:7: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,r2'
[^:]*:8: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,r2'
[^:]*:9: Error: invalid instruction shape -- `vqrshl.s32 q0,q1,r2'
[^:]*:10: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:11: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:22: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
[^:]*:23: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
[^:]*:25: Error: syntax error -- `vqrshleq.s32 q0,q1,q2'
[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshlt.s32 q0,q1,q2'
[^:]*:28: Error: instruction missing MVE vector predication code -- `vqrshl.s32 q0,q1,q2'
[^:]*:30: Error: syntax error -- `vqrshleq.s32 q0,r2'
[^:]*:31: Error: syntax error -- `vqrshleq.s32 q0,r2'
[^:]*:33: Error: syntax error -- `vqrshleq.s32 q0,r2'
[^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshlt.s32 q0,r2'
[^:]*:36: Error: instruction missing MVE vector predication code -- `vqrshl.s32 q0,r2'
